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revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V216A is a family of low voltage 2-Mbit static RAMs organized as 131,072-words by 16-bit, fabricated by Mitsubishi's high-performance 0.25m CMOS technology. The M5M5V216A is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. M5M5V216ATP, RT are packaged in a 44-pin 400mil thin small outline package. M5M5V216ATP (normal lead bend type package) , M5M5V216ART (reverse lead bend type package) , both types are very easy to design a printed circuit board. From the point of operating temperature, the family is divided into three versions; "Standard", "W-version", and "I-version". Those are summarized in the part name table below.
FEATURES
Single +2.7~+3.6V power supply Small stand-by current: 0.3A(3V,typ.) No clocks, No refresh Data retention supply voltage=2.0V to 3.6V All inputs and outputs are TTL compatible. Easy memory expansion by S , BC1 and BC2 Common Data I/O Three-state outputs: OR-tie capability OE prevents data contention in the I/O bus Process technology: 0.25m CMOS Package: 44 pin 400mil TSOP (II)
PART NAME TABLE
Version, Operating temperature Part name
M5M5V216ATP , RT -55L
Power Supply
2.7 ~ 3.6V 2.7 ~ 3.6V
Access time
Stand-by current Icc(PD), Vcc=3.0V typical * Ratings (max.) 25 C --40 C --25 C --1A 40 C --3A 70 C 20A 8A 85 C -----
max.
55ns(@ 2.7V) / 50ns(@3.3V) 70ns(@ 2.7V) / 65ns(@3.3V) 55ns(@ 2.7V) / 50ns(@3.3V) 70ns(@ 2.7V) / 65ns(@3.3V) 55ns(@ 2.7V) / 50ns(@3.3V)
Active current Icc1 (3.0V, typ.)
Standard 0 ~ +70 C
M5M5V216ATP , RT -70L M5M5V216ATP , RT -55H M5M5V216ATP , RT -70H M5M5V216ATP , RT -55LW
0.3A 1A
W-version -20 ~ +85 C
M5M5V216ATP , RT -70LW M5M5V216ATP , RT -55HW M5M5V216ATP , RT -70HW M5M5V216ATP , RT -55L I
2.7 ~ 3.6V 2.7 ~ 3.6V 2.7 ~ 3.6V 2.7 ~ 3.6V
70ns(@ 2.7V) / 65ns(@3.3V) 55ns(@ 2.7V) / 50ns(@3.3V) 70ns(@ 2.7V) / 65ns(@3.3V) 55ns(@ 2.7V) / 50ns(@3.3V) 70ns(@ 2.7V) / 65ns(@3.3V) 55ns(@ 2.7V) / 50ns(@3.3V) 70ns(@ 2.7V) / 65ns(@3.3V)
---
---
--1A --1A
--3A --3A
20A 50A 8A 24A
45mA (10MHz) 5mA (1MHz)
0.3A 1A -----
I-version -40 ~ +85 C
M5M5V216ATP , RT -70L I M5M5V216ATP , RT -55H I M5M5V216ATP , RT -70H I
20A 50A 8A 24A
0.3A 1A
PIN CONFIGURATION
A4 A3 A2 A1 A0 S DQ1 DQ2 DQ3 DQ4 Vcc GND DQ5 DQ6 DQ7 DQ8 WE A16 A15 A14 A13 A12
* "typical" parameter is sampled, not 100% tested.
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BC2 BC1 DQ16 DQ15 DQ14 DQ13 GND Vcc DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC A5 A6 A7 OE BC2 BC1 DQ16 DQ15 DQ14 DQ13 GND Vcc DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A4 A3 A2 A1 A0 S DQ1 DQ2 DQ3 DQ4 Vcc GND DQ5 DQ6 DQ7 DQ8 WE A16 A15 A14 A13 A12
Pin A0 ~ A16 S W OE BC1 BC2 Vcc GND
Function Address input Chip select input Write control input Output inable input Lower Byte (DQ1 ~ 8) Upper Byte (DQ9 ~ 16) Power supply Ground supply
DQ1 ~ DQ16 Data input / output
Outline: TP : 44P3W - H
RT : 44P3W - J
NC: No Connection
MITSUBISHI ELECTRIC
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revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V216ATP,RT is organized as 131,072-words by 16-bit. These devices operate on a single +2.7~3.6V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. The operation mode are determined by a combination of the device control inputs BC1 , BC2 , S , W and OE. Each mode is summarized in the function table. A write operation is executed whenever the low level W overlaps with the low level BC1 and/or BC2 and the low level S. The address(A0~A16) must be set up before the write cycle and must be stable during the entire cycle. A read operation is executed by setting W at a high level and OE at a low level while BC1 and/or BC2 and S are in an active state(S=L). When setting BC1 at the high level and other pins are in an active stage , upper-byte are in a selesctable mode in which both reading and writing are enabled, and lower-byte are in a non-selectable mode. And when setting BC2 at a high level and other pins are in an active stage, lowerbyte are in a selectable mode and upper-byte are in a non-selectable mode. When setting BC1 and BC2 at a high level or S at a high level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S. The power supply current is reduced as low as 0.3A(25 C, typical), and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S BC1 BC2 W OE H L L L L L L L L L L X H L L L H H H L L L X H H H H L L L L L L X X L H H L H H L H H X X X L H X L H X L H Write Read Write Read Mode
Non selection Non selection
DQ1~8
DQ9~16
Icc
High-Z High-Z Standby High-Z High-Z Standby Din Dout High-Z High-Z Din Dout High-Z High-Z Din Dout Din Dout Active Active Active Active Active Active Active Active Active
Write Read
High-Z High-Z
High-Z High-Z
BLOCK DIAGRAM
A0 A1 MEMORY ARRAY 131072 WORDS x 16 BITS A15 A16
CLOCK GENERATOR
High-Z High-Z
DQ 1
DQ 8
-
DQ 9
DQ 16
S BC1 BC2 W GND OE Vcc
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revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND With respect to GND With respect to GND Ta=25 C Standard W-version I-version (-L, -H) (-LW, -HW) (-LI, -HI) Ratings Units
Vcc VI VO Pd Ta Tstg
-0.5* ~ +4.6 -0.5* ~ Vcc + 0.5 0 ~ Vcc 700 0 ~ +70 - 20 ~ +85 - 40 ~ +85 - 65 ~ +150
V mW C C
* -3.0V in case of AC (Pulse width < 30ns) =
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter High-level input voltage Low-level input voltage Conditions
( Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Min Typ Max Vcc+0.3V Units
VIH VIL VOH1 VOH2 VOL II IO Icc1 Icc2
IOH= -0.5mA High-level output voltage 2 IOH= -0.05mA IOL=2mA Low-level output voltage VI =0 ~ Vcc Input leakage current
High-level output voltage 1 Output leakage current Active supply current ( AC,MOS level ) Active supply current ( AC,TTL level )
BC1 and BC2=VIH or S=VIH or OE=VIH, VI/O=0 ~ Vcc
BC1 and BC2 <0.2V , S <0.2V = = > other inputs < 0.2V or = Vcc-0.2V = Output - open (duty 100%) BC1 and BC2=VIL , S=VIL other pins =VIH or VIL Output - open (duty 100%) <1>
> S = Vcc - 0.2V,
2.0 -0.3 * 2.4
Vcc-0.5V
0.6 V 0.4 1 1
A
f= 10MHz f= 1MHz f= 10MHz f= 1MHz
-
45 5 45 5 1 0.3 0.3 0.3 -
60 15 60 15 60 25 30 10 5 2 2 2 0.5
mA
-LW, -LI -L, -LW, -LI -HW, -HI -H, -HW, -HI -H -HW -HI
+70 ~ +85 C +70 C +70 ~ +85 C +40 ~ +70 C +25 ~ +40 C 0 ~ +25 C - 20 ~ +25 C - 40 ~ +25 C
other inputs = 0 ~ Vcc
Icc3
Stand by supply current ( AC,MOS level )
<2>
> BC1 and BC2 = Vcc - 0.2V S < 0.2V = Other inputs=0~Vcc
A
Icc4
Stand by supply current ( AC,TTL level )
BC1 and BC2=VIH , S=VIL Other inputs= 0 ~ Vcc
or
S=VIH
mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for Vcc=3.0V and Ta=25 C
* -3.0V in case of AC (Pulse width < 30ns) =
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
(Vcc=2.7 ~ 3.6V, unless otherwise noted) Limits Typ Units
Min
Max
CI CO
8 10 pF
MITSUBISHI ELECTRIC
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revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS
Supply voltage Input pulse Input rise time and fall time Reference level
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
2.7V~3.6V VIH=2.2V,VIL=0.4V 5ns VOH=VOL=1.5V
Transition is measured 500mV from steady state voltage.(for ten,tdis)
1TTL DQ CL
Including scope and jig capacitance
Output loads
Fig.1,CL=30pF CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits Symbol tCR Parameter Read cycle time Address access time Chip select access time Byte control 1 access time Byte control 2 access time Output enable access time Output disable time after S high Output disable time after BC1 high Output disable time after BC2 high Output disable time after OE high Output enable time after S low Output enable time after BC1 low Output enable time after BC2 low Output enable time after OE low Data valid time after address
M5M5V216ATP,RT - 55 M5M5V216ATP,RT - 70
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min 55
Max 55 55 55 55 30 20 20 20 20
Min 70
Max 70 70 70 70 35 25 25 25 25
ta(A) ta(S) ta(BC1) ta(BC2) ta(OE) tdis(S) tdis(BC1) tdis(BC2) tdis(OE) ten(S) ten(BC1) ten(BC2) ten(OE) tV(A)
10 10 10 5 10
10 10 10 5 10
(3) WRITE CYCLE
Limits Symbol Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to W Byte control 1 setup time Byte control 2 setup time Chip select setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low
M5M5V216ATP,RT - 55 M5M5V216ATP,RT - 70
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE)
Min 55 45 0 50 50 50 50 25 0 0
Max
Min 70 55 0 65 65 65 65 30 0 0
Max
20 20 5 5 5 5
25 25
MITSUBISHI ELECTRIC
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revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle
A0~16
tCR
ta(A) BC1
and / or
tv (A)
ta(BC1)
(Note3)
or
ta(BC2)
(Note3)
BC2
tdis (BC1) or tdis (BC1) ta(S)
S
(Note3)
tdis (S) ta (OE)
(Note3)
OE
(Note3) W = "H" level
ten (OE) ten (BC1) ten (BC2) ten (S)
tdis (OE)
(Note3)
DQ1~16
VALID DATA
Write cycle ( W control mode )
tCW A0~16 tsu (BC1) or tsu(BC2) BC1
and / or
BC2
(Note3)
tsu (S)
(Note3)
S
(Note3)
tsu (A-WH)
(Note3)
OE tsu (A) W tdis(OE) DQ1~16
DATA IN STABLE
tw (W) tdis (W)
trec (W)
ten(OE) ten (W)
tsu (D)
th (D)
MITSUBISHI ELECTRIC
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revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC control mode)
tCW A0~16 tsu (A) BC1
and / or
tsu (BC1) or tsu (BC2)
trec (W)
BC2
S
(Note3) (Note5) (Note3)
W
(Note3)
(Note4) (Note3)
tsu (D) DQ1~16
DATA IN STABLE
th (D)
Write cycle (S control mode)
tCW A0~16
BC1
and / or
(Note4) (Note3)
BC2
tsu (A)
tsu (S)
trec (W)
(Note3)
S
(Note5)
W
(Note3)
(Note4)
tsu (D)
DATA IN STABLE
th (D)
(Note3)
DQ1~16
Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S low , overlaps BC1 and/or BC2 low and W low. Note 5: When the falling edge of W is simultaneously or priorto the falling edge of BC1 and/or BC2 or the falling edge of S, the outputs are maintained in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
MITSUBISHI ELECTRIC
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revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol Parameter Limits Test conditions Min Typ Max Units V V V
Vcc (PD) Power down supply voltage VI (BC) VI (S)
Byte control input BC1 & BC2
Chip select input S
Vcc=3.0V 1) BC1 and BC2 >Vcc - 0.2V = S< 0.2V = other inputs=0~3V 2) S > Vcc - 0.2V = other inputs=0~3V
-LW, -LI -L, -LW, -LI -HW, -HI
+70 ~ +85 C +70 C +70 ~ +85 C
2.0 2.0 2.0 -
1 0.3 0.3 0.3
Icc (PD)
Power down supply current
+40 ~ +70 C -H, -HW, -HI +25 ~ +40 C -H 0 ~ +25 C -HW -HI -20 ~ +25 C -40 ~ +25 C
50 20 24 8 3 1 1 1
A A A A A A A A
Typical value is for Ta=25 C
(2) TIMING REQUIREMINTS
Symbol Parameter Power down set up time Power down recovery time Limits Test conditions Min Typ Max Units ns ms
tsu (PD) trec (PD)
0 5
(3) TIMING DIAGRAM
BC control mode Vcc tsu (PD) BC1 BC2 2.2V BC1 , BC2 > Vcc - 0.2V = 2.7V 2.7V trec (PD) 2.2V
S control mode Vcc tsu (PD) 2.2V S S > Vcc - 0.2V = 2.7V 2.7V trec (PD) 2.2V
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